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IEEE International Workshop
on Digital and Analog Test and Data Analysis

(DATA 2013)

September 12, 2013
Disneyland Hotel, Anaheim, CA, USA

http://DATA.tttc-events.org/

held in conjunction with ITC 2013

CALL FOR PAPERS
Scope -- Submissions -- Key Dates -- Additional Information -- Committees
Scope

Testing of digital logic has made significant improvements in recent years with the use of the stuck-at and delay fault models. Advances in digital test have now led the way to analog and mixed-signal test, looking at analog fault modeling and coverage, testing of I/O interfaces and protocols, and also issues like power droop and crosstalk in digital logic.

New data mining techniques such as outlier analysis and adaptive test have helped to improve quality by exploiting IC defects that have ‘analog’ signatures, even in digital devices. However, our capability for data analysis, defect modeling, simulation, and fault coverage of analog logic has not kept up with capabilities in the digital domain.

All of this means that many of today’s biggest challenges in test are actually analog challenges, and product and test engineers are trying to discover issues that are often hidden within the volumes of “Big Data” in the TB/Hr to TB/Day range that needs to be processed and efficiently mined.

Besides presentations on "classical" digital product engineering, this year’s workshop is intended to focus on new, novel, and leading edge techniques that are being used for data analysis for analog circuits and designs, or for the analog behavior of digital logic. A list of suggested topics for papers and posters to be submitted for this workshop is provided below.
  • Analog Fault modeling and coverage
  • Analog effects in Digital Logic
  • Embedded Instrumentation (iJTAG)
  • Advanced Product Engineering Techniques
  • Product and Project Case studies
  • Advanced dppm reduction techniques
  • Adaptive Test for Product Engineers
  • Data Analysis methods
  • Fault Localization and Diagnosis
  • Yield Learning and Analysis
  • I/O Test, Tuning, and Adjustment
  • Analysis of Aging and Reliability
Submissions

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To present at the workshop, send to JLRoehr@TI.com a PDF version of an extended abstract or a full paper (Max 10 pages, double column, 11pt font size, IEEE proceeding format) by July 12. Each submission should include full name and address of each author, affiliation, telephone number, FAX and Email address. Camera-ready papers for inclusion in the digest of papers will be due on Aug 23. Ideas or proposals for Embedded Tutorials, Debates, Panel Discussions and Poster style “Spot-Light” presentations describing industrial experiences or research are also invited.
Key Dates

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Submission deadline: July 12, 2013
Notification of acceptance: July 22, 2013
Camera Ready Paper (pdf): August 23, 2013
Final Presentation Slides (ppt): September 4, 2013

Additional Information
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Technical Program Submissions:
Jeffrey Roehr
Texas Instruments, USA.
E-mail: JLRoehr@TI.com

General Information:
Arani Sinha
Intel, USA.
E-mail: Arani.Sinha@INTEL.com

Committees
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GENERAL CHAIR
Arani Sinha, Intel

PROGRAM CHAIR
Jeffrey Roehr, Texas Instruments

VICE-PROGRAM CHAIR
Jennifer Dworak, SMU

PANEL CHAIR
Wesley Smith, Galaxy
POSTER CHAIR
Rene Segers, Qualtera
FINANCE CHAIR
Sankaran Menon, Intel
PUBLICITY CHAIR
Kanad Chakraborty, Lattice Semi
PUBLICATIONS CHAIR
Chintan Patel, UMBC
TEST STANDARDS CHAIR
Al Crouch, Asset-Intertech
EU LIAISON
Stefan Eichenberger, NXP

STEERING COMMITTEE
Sankaran Menon, Intel
Adit Singh, Auburn Univ.
M. Tehranipoor, U Connecticut
Hank Walker, Texas A&M
Hans Manhaeve, Q-Star Test
Jim Plusquellic, U. New Mexico

PROGRAM COMMITTEE
Rob Aitken, ARM
Nemat Bidokhti, Cisco
Sreejit Chakravarty, LSI
John Carulli, TI
Patrick Girard, LIRMM, France
Ajay Khoche, Consultant
Mike Laisne, Qualcomm
Amit Nahar, TI
Suriyaprakash Natarajan, Intel 
Jay Orbon, Consultant
John Potter, Asset-Intertech
Rajesh Raina, Freescale
Claude Thibeault, ETS, Canada
Li C. Wang, UCSB
Xiaoqing Wen, KIT, Japan
Qiang Xu, CUHK, Hong Kong

For more information, visit us on the web at: http://DATA.tttc-events.org/

The IEEE International Workshop on Digital and Analog Test and Data Analysis (DATA 2013) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

PAST CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

TTTC 1ST VICE CHAIR
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

SECRETARY
Joan FIGUERAS
UPC Barcelona Tech - Spain
Tel. +
E-mail figueras@eel.upc.edu

ITC GENERAL CHAIR
Doug YOUNG
BVC Industrial - USA
Tel. +1-602-617-0393
E-mail doug0037@aol.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Athens
- Greece
Tel. +30-210-7275145
E-mail dgizop@di.uoa.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
Tel. +33-4-6741-8501
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 2ND VICE CHAIR
Rohit KAPUR
Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
Krish CHAKRABARTY
Duke University - USA
Tel. +1-
E-mail krish@ee.duke.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chen-huan.chiang@alcatel-lucent.com

TECHNICAL ACTIVITIES
Patrick GIRARD
LIRMM – France
Tel.+33 467 418 629
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
Tel. +81 743 72 5221
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc.- USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com